# Ohmforge Logic Simulator (VCD)

> Gate-level netlist + stimuli → event-driven waveforms, timing diagram, VCD and truth table. Simulate a digital circuit written as a small text netlist: gates, tri-state buffers, multiplexers, latches, D/JK/T flip-flops, counters and shift registers with propagation delays and four-valued logic (0, 1, x, z). You get a timing diagram, a timing table, a VCD file for GTKWave or PulseView, setup/hold violations and, for combinational circuits, the truth table.

Part of usefulweb.site (https://usefulweb.site/). Part of [Ohmforge](https://ohmforge.usefulweb.site/) (ownerApp: ohmforge). Results are deterministic calculations from the inputs and the listed assumptions; the API returns exactly what the web page shows.

## Use it
- Human interface: https://ohmforgelogicsimulator.usefulweb.site/ (interactive tool at https://ohmforgelogicsimulator.usefulweb.site/tool)
- JSON API: POST https://ohmforgelogicsimulator.usefulweb.site/api/v1/calculate with a JSON object of inputs (schema: https://ohmforgelogicsimulator.usefulweb.site/api/v1/tool)
- OpenAPI: https://ohmforgelogicsimulator.usefulweb.site/openapi.json
- MCP (Streamable HTTP): https://ohmforgelogicsimulator.usefulweb.site/mcp - tool `ohmforge_logic_simulator`

## Inputs
- netlist (textarea): Netlist - Native format or a structural Verilog subset (one module of single-bit nets: input/output/wire/reg, gate primitives, assign with & | ^ ~ ?: and #delay, always @(posedge clk [or posedge rst]) with <= and if/else; stimuli then go into the extra lines). Native format, one statement per line. Elements: TYPE NAME then nets (output first) or PIN=net, plus delay=N (or rise=/fall=), e.g. "and U1 Y A B delay=2", "dff F1 Q=q D=d CLK=clk RST=r setup=3". Types: and or nand nor xor xnor not buf bufif1 bufif0 notif1 notif0 mux2 mux4 dlatch srlatch dff jkff tff counter shiftreg. Sources: input, clock NET period=10 duty=0.5, stim NET 0:0 10:1, count A B period=10, const NET 1. Also output, bus, timescale, duration, name. # starts a comment.
- stimuli (textarea): Extra stimulus lines (optional) - Appended to the netlist, e.g. "stim A 0:0 15:1 30:x". Handy for trying other inputs on the same circuit.
- duration (integer): Duration (time units, 0 = from the netlist) - Integer time units of the timescale. 0 uses the netlist's duration line, the end of a count pattern, or 1.25 × the last stimulus.
- signals (text): Signals to show (optional) - Comma-separated net or bus names for the diagram and table; empty shows all. The VCD always contains every net.

## Method
- Event-driven simulation on integer time units: a time-ordered event queue applies driver changes, resolves each net from all its drivers (z yields, equal values agree, a conflict gives x) and re-evaluates only the elements that read a changed net. Zero-delay feedback is iterated as delta cycles (max 1000 per time step).
- Gates follow the four-valued tables of IEEE 1364: a 0 on an AND input forces 0, a 1 on an OR input forces 1, otherwise x/z inputs give x. Tri-state buffers drive z when disabled and x when the enable is unknown.
- Delays are inertial, as for Verilog gate primitives: a pulse shorter than the gate delay is swallowed. rise= and fall= set separate delays for transitions to 1 and to 0.
- Flip-flops act on the 0→1 clock edge (edge=neg for 1→0); an edge through x makes the output x unless it would not change. Asynchronous RST/SET are active high. Power-up state is x unless init= is given. setup= and hold= mark a data change too close to the edge as a violation and drive x; real metastability (random resolution after a delay) is not modelled.
- The Verilog subset is translated to the same elements: assign expressions become gates (the #delay on the gate that drives the target), always blocks with nonblocking assignments become D flip-flops whose D input is a multiplexer tree built from the if/else branches; an "if (rst)" branch with constant assignments becomes an asynchronous reset or set. Vectors, parameters, initial blocks and hierarchy are rejected with the line number.
- Truth tables (combinational circuits with up to 6 inputs) simulate every input combination until the circuit settles. The VCD export follows IEEE 1364-2005 clause 18 (header, $var wire per net and per bus, $dumpvars at #0) without a $date line, so identical input gives an identical file.

## Limits
- Logic-level simulation with fixed integer delays: no analogue behaviour, no fan-out or load-dependent delays, no real metastability. Use it to understand timing and to check logic, not to sign off a hardware design.