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Ohmforge Logic Simulator (VCD)

Gate-level netlist + stimuli → event-driven waveforms, timing diagram, VCD and truth table.

Native format or a structural Verilog subset (one module of single-bit nets: input/output/wire/reg, gate primitives, assign with & | ^ ~ ?: and #delay, always @(posedge clk [or posedge rst]) with <= and if/else; stimuli then go into the extra lines). Native format, one statement per line. Elements: TYPE NAME then nets (output first) or PIN=net, plus delay=N (or rise=/fall=), e.g. "and U1 Y A B delay=2", "dff F1 Q=q D=d CLK=clk RST=r setup=3". Types: and or nand nor xor xnor not buf bufif1 bufif0 notif1 notif0 mux2 mux4 dlatch srlatch dff jkff tff counter shiftreg. Sources: input, clock NET period=10 duty=0.5, stim NET 0:0 10:1, count A B period=10, const NET 1. Also output, bus, timescale, duration, name. # starts a comment.

More options

Appended to the netlist, e.g. "stim A 0:0 15:1 30:x". Handy for trying other inputs on the same circuit.

Integer time units of the timescale. 0 uses the netlist's duration line, the end of a count pattern, or 1.25 × the last stimulus.

Comma-separated net or bus names for the diagram and table; empty shows all. The VCD always contains every net.

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Try an example: Half adder with gate delays (XOR glitch window) · 4-bit ripple counter: transient wrong counts · Synchronous counter, shift register and a setup violation · Tri-state bus contention resolves to x · 2-bit counter written in the Verilog subset

More about this tool

How it works

Simulate a digital circuit written as a small text netlist: gates, tri-state buffers, multiplexers, latches, D/JK/T flip-flops, counters and shift registers with propagation delays and four-valued logic (0, 1, x, z). You get a timing diagram, a timing table, a VCD file for GTKWave or PulseView, setup/hold violations and, for combinational circuits, the truth table.

  • Event-driven simulation on integer time units: a time-ordered event queue applies driver changes, resolves each net from all its drivers (z yields, equal values agree, a conflict gives x) and re-evaluates only the elements that read a changed net. Zero-delay feedback is iterated as delta cycles (max 1000 per time step).
  • Gates follow the four-valued tables of IEEE 1364: a 0 on an AND input forces 0, a 1 on an OR input forces 1, otherwise x/z inputs give x. Tri-state buffers drive z when disabled and x when the enable is unknown.
  • Delays are inertial, as for Verilog gate primitives: a pulse shorter than the gate delay is swallowed. rise= and fall= set separate delays for transitions to 1 and to 0.
  • Flip-flops act on the 0→1 clock edge (edge=neg for 1→0); an edge through x makes the output x unless it would not change. Asynchronous RST/SET are active high. Power-up state is x unless init= is given. setup= and hold= mark a data change too close to the edge as a violation and drive x; real metastability (random resolution after a delay) is not modelled.
  • The Verilog subset is translated to the same elements: assign expressions become gates (the #delay on the gate that drives the target), always blocks with nonblocking assignments become D flip-flops whose D input is a multiplexer tree built from the if/else branches; an "if (rst)" branch with constant assignments becomes an asynchronous reset or set. Vectors, parameters, initial blocks and hierarchy are rejected with the line number.
  • Truth tables (combinational circuits with up to 6 inputs) simulate every input combination until the circuit settles. The VCD export follows IEEE 1364-2005 clause 18 (header, $var wire per net and per bus, $dumpvars at #0) without a $date line, so identical input gives an identical file.

Logic-level simulation with fixed integer delays: no analogue behaviour, no fan-out or load-dependent delays, no real metastability. Use it to understand timing and to check logic, not to sign off a hardware design.

Sources

Part of Ohmforge

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Related tools

How to use the Ohmforge Logic Simulator

Simulate a gate-level netlist with delays and 0/1/x/z values, read the timing diagram and timing table, spot glitches and export a VCD file.

What it is for

A truth table tells you what a circuit computes once everything has settled. It says nothing about the time in between. This tool shows that time. You describe a circuit as a short text netlist, one element per line, give the inputs a stimulus, and an event-driven simulator works out every change on every net, with each gate's propagation delay.

Use it to see why a ripple counter shows wrong values for a few nanoseconds, how a flip-flop reacts when data changes too close to the clock, or what a shared bus does when two tri-state drivers are on at the same time. Nets can be 0, 1, x (unknown) or z (not driven). You get a timing diagram, a timing table, a VCD file and, for small circuits without flip-flops, a truth table.

It is a logic-level simulator with whole-number delays. It does not simulate voltages, loads or real metastability.

Worked example

Load the example 4-bit ripple counter: transient wrong counts. Four T flip-flops with T tied to 1 are chained: F0 runs on the 10 ns clock, and each later stage toggles on the falling edge of the stage before it. Every flip-flop has delay=2, and reset is high until 3 ns.

The run takes 170 ns and needs 72 events. The bus lane Q reads 0 from 2 ns (after reset), 1 at 7 ns, then 0 at 17 ns, and only reaches 2 at 19 ns. Going from 3 to 4 is worse: 3 at 27 ns, then 2 at 37, 0 at 39 and 4 at 41 ns. From 7 to 8 the bus passes through 6, 4 and 0 before it settles on 8 at 83 ns, 8 ns after the clock edge. Logic that decodes Q directly would see those false values as real glitches. That is why designs use synchronous counters.

How to read the result

  • Timing diagram: one lane per net. Buses (counters, shift registers or bus lines) show their decimal value in boxes. A red band means x, a dashed middle line means z.
  • Timing table: the same data as text, with one row for each time at which any shown signal changes.
  • Truth table: only for circuits without flip-flops and with up to six inputs. Every input combination is simulated, and the time it takes to settle is listed.
  • Timing violations: setup and hold problems you asked for with setup= or hold=. The affected output becomes x.
  • VCD file: the full waveforms of every net, timescale included.

Tips and common mistakes

  • Flip-flops and counters start at x. Drive a reset, or give them init=0.
  • Delays are inertial: a pulse shorter than a gate's delay disappears, as with Verilog gate primitives. Use rise= and fall= when the two edges differ.
  • A loop through gates with delay=0 cannot settle and is reported. Give one gate in the loop a delay of at least 1.
  • count A B C period=10 steps the inputs through all combinations, with the first net as the most significant bit.
  • Use Signals to show to keep the diagram readable; the VCD keeps every net.

FAQ

Does it model metastability?

No. A setup or hold violation turns the output into x, so you can see which paths are affected. A real flip-flop would settle to 0 or 1 after a random time, and that is not simulated.

Which tools open the VCD file?

Any viewer for the IEEE 1364 value change dump format, such as GTKWave, PulseView or Surfer. Buses appear as vectors next to their bits.

Can I use my schematic or Verilog?

Yes. In the workbench, Instruments → Logic simulator… imports the gates of the open schematic or builds a circuit from a Boolean expression. The netlist box also accepts a structural Verilog module with single-bit nets.

What does x on an output mean?

The simulator cannot decide between 0 and 1. Common causes are an uninitialised flip-flop, an undriven input (z), two drivers fighting, or a timing violation.

Guide last updated:

For scripts and AI agents

  • JSON API: POST https://ohmforgelogicsimulator.usefulweb.site/api/v1/calculate (same calculation as this page)
  • Interface description: OpenAPI 3.1 · AI guide: llms.txt
  • MCP server (Streamable HTTP): https://ohmforgelogicsimulator.usefulweb.site/mcp · tool name ohmforge_logic_simulator
Example request
curl -s -X POST https://ohmforgelogicsimulator.usefulweb.site/api/v1/calculate \
  -H 'content-type: application/json' \
  -d '{"netlist":"name Half adder\ninput A B\noutput S C\nxor U1 S A B delay=2\nand U2 C A B delay=1\ncount A B period=10"}'
Feedback · ideas & bug reports welcome